The invention relates to a synchronous semiconductor device, and in particular, to a method of latching an input signal to a synchronous semiconductor device.
In a synchronous semiconductor device such as synchronous dynamic random access memory (SDRAM), there are demands for reducing the set-up time and the set-up/hold time for input signals (command signal and address signal) which follow a clock signal in order to accommodate for the acceleration of the synchronous clock cycle.
Japanese Unexamined Patent Publication No. Hei 8-17182 discloses a synchronous semiconductor device according to a first prior art. A decoder which precedes a latch circuit is provided in the semiconductor circuit to enable a rapid internal operation. As a consequence, the decoding rate of the decoder has a direct influence upon the set-up/hold time.
The first prior art semiconductor device includes a logic circuit disposed between an external command input terminal and the latch circuit. The logic circuit decodes an external command signal fed to each external command input terminal, and the decoded signal is held by the latch circuit in synchronism with the clock signal. This technique is commonly referred to as xe2x80x9ccommand prefetch approachxe2x80x9d.
FIG. 1 is a block diagram of a command decoder circuit 60 of a synchronous semiconductor device according to a second prior art. The command decoder circuit 60 operates according to the command prefetch approach. Specifically, the command decoder circuit 60 includes a decode circuit 51 connected between four external command input terminals T1-T4 and a latch circuit 50. The decode circuit 51 includes a decode unit 52 having six AND circuits 52a-52f, and four input buffers 53a-53d. Clock signal CLK is fed to an external clock signal input terminal T0 and passed through a clock buffer 54 to the latch circuit 50. External command signals applied to the input terminal T1-T4 are passed through corresponding input buffers 53a-53d, respectively, to the decode unit 52, which then decodes the external command signals to provide decoded signals, which are in turn received and held by the latch circuit 50 in synchronism with the clock signal CLK.
FIG. 2 is a block diagram of one of the input buffers 53a-53d. Thus any one of the input buffers 53a-53d includes a level conversion circuit 56, a delay circuit 57 connected to the level conversion circuit 56, an inverter circuit 58 connected to the delay circuit 57 and an inverter circuit 59 connected to the inverter circuit 58. In each of the input buffers 53a-53d, the delay circuit 57 controls the signal input to the decode unit 52, whereby the set-up/hold time for each external command input terminal T1-T4 is controlled.
Japanese Unexamined Patent Publication No. Hei. 9-153279 discloses a semiconductor device according to a third prior art. This semiconductor device also includes a decoder which precedes a latch circuit. Specifically, the semiconductor device includes a plurality of external command input terminals, D-type flip-flop circuits each for temporarily storing one of a plurality of external command signals applied to the plurality of external command input terminals, and a plurality of command decode circuits. The D-type flip-flop circuits deliver the plurality of external command signals which they temporarily store to the respective command decode circuits. The plurality of command decode circuits operate to decode the external command signal delivered from the D-type flip flop circuit to provide decoded signals, which are then supplied to a plurality of latch circuits to be held therein. At this time, a clock signal which depends on the delay time of an associated command decode circuit is fed to each latch circuit, thus enabling it to latch the decoded signal in accordance with the corresponding clock signal.
The first prior art semiconductor device has an access time which is more rapid than the access time of a semiconductor device in which a latch circuit precedes a logic circuit. However, a decoder having multiple stages of circuits and elements is connected between the external command input terminal and the latch circuit, and this results in a relatively long time interval or delay time from a point in time when an external command signal is applied to an external command input signal until the logic circuit delivers a decoded signal by decoding the external command signal. As a consequence, the set-up/hold dead zone of the decoded signal relative to the clock signal will be offset toward the set-up side. In other words, the set-up time of the decoded signal will be shortened.
With the semiconductor device according to the first prior art, the delay time within the logic circuit varies from decoded signal to decoded signal as a result of the potential transition situation of the external command input terminals and operational noises of the semiconductor device.
Consequently, the total dead zone in the set-up/hold of the decoded signal relative to the clock signal further increases.
By contrast, in the command decoder circuit 60 shown in FIG. 1, the delay circuit 57 controls the set-up/hold time for each external command terminal. However, a delay time from the transition of the potential of the signal applied to each external command input terminal T1-T4 to the transition of a potential occurring in the decoded signal from each of AND circuits 52a-52f varies from decoded signal to decoded signal. In addition, the delay time of the decoded signal D1-D6 changes depending on the direction of transition of the potential on each external command input terminal T1-T4 (i.e, from H level to L level or from L level to H level).
In addition, the delay time of the decoded signal D1-D6 changes due to operational noises of the semiconductor device such as a variation in the supply voltage, for example. By way of example, if the command decoder circuit 60 is used in a synchronous DRAM, the following difficulties are experienced:
A mode register set command or self-refresh command is applied to a semiconductor device during its idle condition where the operational noises of the semiconductor device remain relatively low. By contrast, an active command, a read/write command or a precharge command is applied to the semiconductor device during its active condition where the operational noises are relatively high. Accordingly, with the active command, the read/write command and the precharge command, a variation in the set-up/hold time attributable to noises in the AND circuits 52a-52f of the decode unit 52 is greater than a corresponding variation experienced by the mode register set command or the self-refresh command. In other words, there is a large variation in the set-up/hold time between different processing commands.
It is difficult to adjust such variation by using a plurality of delay circuits 57 in each of the input buffers 53a-53d which precedes the decode unit 52. Specifically, to accommodate for such variation, it would be necessary to choose an individual delay time for each of the plurality of delay circuits 57, but in practice, such control would be difficult, and there remains a certain variation, which causes the dead zone breadth of the set-up/hold to increase when viewed from the whole assembly of external command input terminals T1-T4. If the command decoder circuit 60 is used in an address decode circuit or a variety of test mode decision circuits, a similar problem occurs.
For a semiconductor device including the input buffers 53a-53d as shown in FIG. 2, there is a difference between a positive logic output circuit and a negative logic output circuit in the number of stages of constituting circuit elements. Obviously, there results an offset in the output timing between the positive logic output circuit and the negative logic output circuit, and this leads to an offset between the operations of AND circuits 52a-52f which receive complimentary logic signals. Specifically, with the AND circuits 52a-52f, when producing a decoded output signal having an L level (or when selecting two input signals each having an L level), the transition of the decoded output signal is fastest while degrading the hold time. On the contrary, when producing a decoded output signal having an H level (or when selecting two input signals each having an H level), the transition of the decoded output signal is slowest while degrading the set-up time.
The latch circuit 50 includes latches 50a-50f each associated with AND circuits 52a-52f. 
On the other hand, in the semiconductor device according to the third prior art, while the delay time can be adjusted for each external command terminal, the set-up/hold time for each external clock signal is determined by the D-type flip-flop circuit. In other words, it is impossible to adjust the set-up/hold time for each command with the semiconductor device according to the third prior art.
Furthermore, in the semiconductor device according to the third prior art, each command decode circuit follows the D-type flip-flop circuit. Each latch circuit latches an output signal from the corresponding command decode circuit, and at this end, each latch circuit is supplied with a clock signal which takes the delay time into consideration. However, such clock signal is required to have the same delay time as the set-up/hold window width that is determined by the D-type flip-flop circuit. In addition, it is necessary to provide a number of clock signal generator circuits which is equal to the number of the latch circuits. Because the clock signal generator circuit requires a relatively increased number of elements, it follows that the circuit area for a synchronous DRAM, which is provided with a number of commands and address, decodes increases.
It is an object of the invention to provide a synchronous semiconductor device that is compact and has an improved set-up/hold time.
To achieve the above object, the present invention provides a synchronous semiconductor device including a decoder, a delay adjusting unit, and a latch circuit unit. The decoder receives a plurality of input signals and produces a plurality of decoded signals. The delay adjusting unit is connected to the decoder and adjusts a delay time of each of the decoded signals and provides a plurality of adjusted decoded signals. The latch circuit unit is connected to the delay adjusting unit and latches the adjusted decoded signals in synchronism with a clock signal. The decoder typically includes a plurality of decode circuits, and the delay adjusting unit includes a plurality of delay adjusting circuits, each of which is connected with each of the decode circuits. The latch circuit unit includes a plurality of latch circuits, each of which is connected with each of the delay adjusting circuits. The input signal includes one of an address signal and a command signal used to operate a synchronous semiconductor memory. One of the decoded circuits will operate when the input signal is decoded. The synchronous semiconductor device further includes a plurality of command input terminals for receiving the command input signals.
The delay adjusting circuit includes an input terminal to which the decoded signal is provided, an output signal from which the decoded signal is output, at least one switching element connected to at least one node between the input terminal and the output terminal, and at least one capacitor, which can be a MOS capacitor, connected to the switching element and the ground. The delay adjusting circuit adjusts the delay time of the associated decoded signals depending on the operational condition of the synchronous semiconductor device, and the delay time is changed when the switching element is switched.
The synchronous semiconductor device described above is used to latching a plurality of input signals. The input signals are first decoded to provide decoded signals. The delay time of each of the decoded signals is adjusted so that a variation in the set-up/hold time for the decoded signals is reduced, thus providing adjusted decoded signals. The adjusted decoded signals are then latched in synchronism with a clock signal. The delay time of each decoded signal is adjusted depending on the operational condition of the synchronous semiconductor device.
Other aspects and advantages of the present invention will become apparent from the following description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.